OSIRIS schematic porting

Fast and efficient schematic migration is an essential tool for evaluating full-chip and IP core target processes. Simulating migrated circuits using new PDK components and assessing performance in new processes is crucial for IP companies that need to license analog cores to new customers in unfamiliar processes. I will.

OSIRIS mapping, placement, and rewiring capabilities go far beyond the capabilities of a simple component swapper. The interactive GUI finds circuit symbols in the source design, guides you in mapping pins and parameters to target symbols, and reference libraries such as standard cells can be replaced with new foundry versions.

Physical differences between PDKs, such as cell origin, symbol size, and pin differences, are automatically resolved. The rewiring tool allows you to add new pins and connect them to the specified net, but the wires from the deleted pins are removed from the circuit. Component checking and rewiring migrates the complete circuit hierarchy in a single pass.

The complexity of property conversion between the source PDK and the target PDK is handled automatically without the user having to convert between types. You can call an optional recalculation to adjust the physical parameters to keep the passive values.

Pin and parameter mapping

The task of mapping pins and parameters between PDKs is greatly simplified by the OSIRIS graphical interface. Information from the original PDK and the new PDK is identified and presented to the user in a clear format for easy mapping and conversion. These value settings can be changed from simple scaling to complex relationships as needed.

Pins are automatically rerouted as part of the migration process to ensure a secure connection, even if the symbol size and pin position are different.

The property type is automatically converted during the migration process to ensure that the parameters exactly match the requirements of the new PDK. Advanced parameter assignment and callback triggering capabilities allow you to transform even the most complex components against core parameters and additional simulation and layout constraints.

Features and features

OSIRIS SMT has many features that make it the most powerful and versatile schematic migration tool on the market. From interactive component mapping to automatic rewiring and short locations, OSIRIS tools can migrate the most complex designs between IDM and custom foundry PDKs.

The advanced features of the Cadence database, such as hierarchical parameters and netlist properties, are fully preserved, providing a fully migrated schematic that includes all the features of the original design.

Interactive schematic comparison

It is important to ensure that the schematics migrated for the purpose of schematic migration maintain circuit integrity. OSIRIS has a dedicated migration comparison tool that checks the placement, connectivity, and parameters of the target circuit to make sure it matches the original circuit.

Schematic comparisons, unlike LVS tools, take into account differences in component names, parameter types, and values to instantly identify discrepancies between old and new circuits. Problems such as maximum / minimum size violations and component congestion are reported and highlighted within the schematic editor for easy identification and resolution.

Fast and hierarchical migration

OSIRIS migrations can handle a single cell, a defined hierarchy, or an entire design in a single path. You can map the reference library to a flow so that the entire design is udpated to use the symbols and standard cells of the new process.

Scaling and grid Force

The new PDK has large symbols and different database units that may need to be resolved during the migration process. OSIRIS can add user-defined scale and grid elements during migration to apply new PDK constraints.

Automatic symbol offset

OSIRIS automatically recognizes the offset between the source and target symbols and adjusts the symbol's position to align correctly with the circuit wiring. Offsets between primitive components and standard cell libraries are resolved without the need for user calculations. Saves the hassle of entering offset information for potentially hundreds of components.

Automatic pin rewiring

Changes in symbol size and pin position between PDKs mean that the symbol pins are not aligned with the wiring. This is detected during the migration process and reconnects the wires if there is a large difference in size between the old and new symbols, or if a pin moves within the symbol.

Rewiring the short circuit location

The added pins of the new component can be short-circuited to the existing wiring, damaging the functionality of the circuit. OSIRIS finds these shorts during the migration process and automatically rewires the wires around them.

Remove redundant wiring

The new symbol may have fewer pins than the original PDK, which is a problem with unconnected wires in the new schematic. OSIRIS finds and removes redundant wiring as part of the migration process and warns the schematic of open wires.

Flow customization

OSIRIS allows full flow customization within the Cadence toolset using the Skill ™ programming language. Optional extension routines allow users to fine-tune the migration flow to manage complex circuit elements and adapt to special requirements.

OSIRIS extension routines are automatically called as part of the migration process to allow you to migrate circuit hierarchies in a single pass.

Whether it's an IP core or a full chip, IN2FAB's OSIRIS technology enables rapid porting of existing analog mixed-signal IP in the time required to redesign in just a fraction of the time and cost.

Email: info@TokyoNF.com

Phone: 070-1360-8586