The design services project consists of a three-step process that enables flexible and efficient tasks and the high reliability of ported silicon.

Design feasibility analysis

Design analysis explores and reports on the three elements of a migration project: design data, source technology, and target processes. The name and parameters of each source component are identified from the original circuit and mapped to alternatives to the target process technology. Each component type is documented in the feasibility documentation and the differences between the source and target devices are reviewed.

IN2FAB's Porting Project Analysis provides a comprehensive review of source data and requirements for migration to new processes or foundries, while Design Analysis provides a complete picture of the project's overall cost and schedule.

Project implementation

Performed by IN2FAB project engineers using OSIRIS porting technology. The library uses Cadence Design Tools. The library structure and all circuit components, including parameterized cells and other design objects, are preserved. According to the agreed schedule, engineers will use the extracted parastic data to simulate important subcircuits in a fast cycle.

The schematic is usually processed first and made available at the beginning of the project for early simulation. Layout hierarchy data is ported and validated using the design hierarchy to ensure that each section of the database is DRC and LVS clean prior to shipment.

The schematic and layout data and library hierarchy of the ported design match the source. Advanced complex components such as layers, components, hierarchies, and Virtuoso XL ™ information are transferred as part of the porting process, giving you a new layout that you can send directly to editing or manufacturing.

Design delivery

The schedule is defined at the beginning of the project and the IN2FAB project manager will deliver the ported data on time.

The final database is checked against decks fed by the target foundry through DRC and LVS validation. Design subsections can be pre-examined on a pre-agreed schedule so that post-layout simulations can be performed in critical areas of the circuit.

The final delivery includes a complete database with both schematic and layout data migrated to the target process.